| PTP/IEEE 1588 |
| LP mode | Multicast |
| agreement | UDP/IPv4; ETH |
| Delay mechanism | End-to-end, peer-to-peer |
| IP address method | DHCP |
| RJ-45 Ethernet | 10/100 Mbit Ethernet connection; only for synchronization, no data transfer
possible. |
| Programmable correction limit | 10 ns to 500 ms |
| IRIG input indicator |
| Compatible codes | IRIG code A or B; AM or DC |
| Compatibility (AM code) | 0.5 Vp-p to 10 Vp-p |
| Compatibility (DC code) | DC level shift (edge detection); TTL/CMOS compatible |
| Low:<1.5 V | High:>3.5V |
| impedance | 20 kΩ |
| Insulation voltage | 350V DC |
| Interface | BNC |
| Digital l/O indicators |
| Number of channels | eight |
| Compatibility (input) | CMOS/TTL,weak pull-up 100 kQto+5 V |
| Low:<0.8 V High:>2.0V |
| Compatibility (output) | TTL, 20 mA |
Overvoltage protection
- Input mode
- Output mode | ±30 V
-0.5 to +5.5 V; short circuit protected |
| Interface | D-SUB-15 socket |
| Counter indicator |
| Number of channels | 1 advanced counter or 3 digital inputs |
| counter mode | Event counting | Basic event counting, gated counting, up/down counting and encoder mode
(X1,X2 and X4) |
| Waveform timing | Period, frequency, pulse width, duty cycle and edge separation |
| Sensor modes | Encoder(angle and linear), gear tooth with/without zero, gear tooth with miss-
ing/double teeth |
| Input signal compatibility | CMOS/TTL |
| Counter resolution | 32-bit |
| Counter time base | 80 MHz |
| Time base precision | Typical 10 ppm(DEWE2); 2 ppm(DEWE3); (defined by the backplane) |
| Maximum input frequency | 10 MHz |
| Overvoltage protection | ±30 Voc,50 Vpek(for100 ms) |
| Sensor supply | 5V(600 mA)and 12V(600 mA) |
| Interface | On same D-SUB-15 socket as Digitall/O |
